First, the polynomial itself and its table of feedback terms. The polynomial is X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0 Note that we take it "backwards" and put the highest-order term in the lowest-order bit. The X^32 term is "implied"; the LSB is the X^31 term, etc. The X^0 term (usually shown as "+1") results in the MSB being 1. added CCITT (X^16+X^12+X^5+X^0) and CRC-16 (X^16+X^15+X^2+X^0) polynomials (Heinz Repp, Feb 4 1997)
Note that the usual hardware shift register implementation, which is what we're using (we're merely optimizing it by doing eight-bit chunks at a time) shifts bits into the lowest-order term. In our implementation, that means shifting towards the right. Why do we do it this way? Because the calculated CRC must be transmitted in order from highest-order term to lowest-order term. UARTs transmit characters in order from LSB to MSB. By storing the CRC this way, we hand it to the UART in the order low-byte to high-byte; the UART sends each low-bit to hight-bit; and the result is transmission bit by bit from highest- to lowest-order term without requiring any bit shuffling on our part. Reception works similarly.
The feedback terms table consists of 256, 32-bit entries. Notes:
- The table can be generated at runtime if desired; code to do so is shown later. It might not be obvious, but the feedback terms simply represent the results of eight shift/xor opera- tions for all combinations of data and CRC register values.
- The CRC accumulation logic is the same for all CRC polynomials, be they sixteen or thirty-two bits wide. You simply choose the appropriate table. Alternatively, because the table can be generated at runtime, you can start by generating the table for the polynomial in question and use exactly the same "updcrc", if your application needn't simultaneously handle two CRC polynomials. (Note, however, that XMODEM is strange.)
- For 16-bit CRCs, the table entries need be only 16 bits wide; of course, 32-bit entries work OK if the high 16 bits are zero.
- The values must be right-shifted by eight bits by the "updcrc" logic; the shift must be unsigned (bring in zeroes). On some hardware you could probably optimize the shift in assembler by using byte-swap instructions.
